[Compgeom-announce] Subject: UMIACS Workshop on Parallelism in Algorithms andArchitecture, May 12

[Michael Bender <bender@cs.sunysb.edu>]

Workshop on Parallelism in Algorithms and Architectures

Date: Friday, May 12, 2006

Location: Room CSIC 1121, Computer Science Classroom Building
University of Maryland, College Park


Tentative Schedule


8:30-10:00 Morning session

- G. Lowney, Intel: Why Intel is designing multi-core processors

- J. Moreno, IBM: Chip-level integration: the new frontier for
microprocessor architecture

- U. Vishkin, University of Maryland:  PRAM-on-Chip: some current issues


10:00-10:30 Coffee break


10:30-12:00 Late morning session

- B. Falsafi, Carnegie-Mellon University: TBA

- J. Reif, Duke University: Experimental Demonstrations of Parallel
Computation at the Molecular Scale

- V. Ramachandran, University of Texas, Austin: Cache-Oblivious Gaussian
Elimination Paradigm


12:00-1:45 Lunch break


1:45-3:15 Afternoon session

- M. Bender,  SUNY Stony Brook: An Adaptive Packed-Memory Array

- C. Scheideler, TU Munich: Distributed coloring in O(sqrt{log n}) bit
rounds

- R. Kleinberg, University of California, Berkeley and Cornell
University: Geographic Routing in Hyperbolic Space



Registration is free, but space is limited.
If you are interested, please register at your earliest convenience
through:

https://conferences.umiacs.umd.edu/paa/registration.html


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